1. Field of the Invention
The field of this invention relates to a planar process and structure for use in MSI and LSI structures, and more particularly relates to Gallium Arsenide integrated circuit fabrication using a planar technology in conjunction with selective ion implantation. In addition a new structure is described which improves the JFET and MESFET device speed.
In silicon integrated circuit fabrication the planar process has led to medium scale and large scale fabrication technology used extensively in modern electronics. For Gallium Arsenide integrated circuit fabrication, however, a planar technology was not readily available although even before Germanium and Silicon became important, compound semiconductors were the object of much interest, particularly in the so called three-five compounds of which Gallium Arsenide has proven to be the most important. Gallium Arsenide is a material whose characteristics are closely related to those of Germanium since Gallium is a third column neighbor and Arsenic is the fifth column neighbor of Germanium in the periodic table thus acquiring the label III-V compound. Gallium Arsenide possesses a direct type of band structure and has high electron mobility and a large band gap, and is superior to silicon in many respects. The high vapor pressure of arsenic makes production of Gallium Arsenide, at least at the electronic grade, extremely difficult. Czochralski techniques using high pressure chambers have been unsatisfactory. Horizontal furnaces using zone refining techniques have proven to be more satisfactory with the resulting material still not totally acceptable due to inferior structural perfection. Use of compound materials particularly in the area of fabrication of switching parametric diodes and hot electron or "Gunn" effect current limiters is for the same reason difficult and unreliable. It is clear then that the advantages of a planar structure and process lie in the ease of integrated circuit fabrication with regard to Gallium Arsenide substrates and would result in increased device and circuit reliability when creating isolated depletion and enhancement mode JFETS and MESFETS, unijunction and Schottky barrier diodes, resistors and hot electron current limiters. Further, the elimination of stepheights which of necessity must be traversed by metal connections and diffusions through the planar process has been an advantage aptly demonstrated by silicon as well as other single element integrated circuit fabrication technology. Due to the problems heretofore pointed out with regard to III-V compounds and in particular Gallium Arsenide, deposition of photoresist and development as well as deposition of insulating layers such as silicon dioxide and silicon nitride have been difficult to control in optimum processing environments.
2. Prior Art
In silicon integrated circuit fabrication technology the planar process has led to medium scale (MSI) and large scale integration (LSI) now extensively used in modern electronics. However, Gallium Arsenide integrated circuit fabrication has been limited to the etched mesa structure due to the different processing steps required and planar technology has not been applied to semi-insulating GaAs substrates. The GaAs techniques in the prior art required fabrication using a mesa structure which was etched out, leaving stepheights to be traversed by metal interconnections and diffusions, thereby subjecting such traversing layers to stress and possible fracture as well and providing a region for the collection of processing debris. The foregoing problems have resulted in lower yields as well as a decrease in device and circuit reliability avoided by the instant invention.
In addition to the foregoing prior processing techniques limited the size of the particular structure involved thereby restricting the minimum dimensions thereof to that obtainable through optical means and essentially fixed the speed of such devices at a particular limit.